1. Field of the Invention
The present invention relates generally to dynamic random access memory devices, and more particularly, to improvement of a dynamic random access memory device having a self refresh mode.
2. Description of the Background Art
A dynamic random access memory (referred to as "DRAM" hereinafter) having a memory cell formed of one switching transistor and one data storing capacitor is widely used as a semiconductor memory suitable for increase in integration density in a semiconductor substrate. Because a DRAM holds a data signal by a capacitor, it is necessary to amplify periodically the data signals stored in the capacitor, i.e. a refresh operation must be carried out. Almost all of the recent DRAMs have a function to carry out refresh operation without needing an internal or external refresh control (generally called "a self refresh function"). An example of a DRAM including a self refresh feature is disclosed in U.S. Pat. No. 4,933,907 granted to the applicant of the present application. A document entitled "MITSUBISHI LSIs" (October 1991; pp. 1/28-10/28, 20/28) discloses a more specific self refresh operation in a DRAM.
FIG. 7 is a block diagram of a DRAM for showing the background of the present invention. Referring to FIG. 7, a DRAM 100 includes a memory cell array 1 including 4,718,592 memory cells arranged in rows and columns, a row decoder 2 for selecting a word line in memory cell array 1, a column decoder 3 for selecting a column of a memory cell to be accessed, an address buffer 4 for receiving address signals A0-A9 externally applied in a time divisional manner, a sense refresh amplifier 5 connected to a bit line in memory cell array 1, and an IO gate circuit 6 responsive to an output signal of column decoder 3 for selectively connecting a bit line in memory cell array 1 with an input buffer 7 and an output buffer 8. In FIG. 7, line 100 also indicates a semiconductor substrate.
A clock signal generator 9 responds to an externally applied row address strobe signal /RAS and a column address strobe signal /CAS to generate various clock signals for controlling a circuit in DRAM 100. Refresh control circuit 10 operates in response to a refresh control signal CBR provided from clock signal generator 9 to generate a refresh address signal RFA.
In writing operation, externally applied data signals DQ0-DQ8 are provided to IO gate circuit 6 via input buffer 7. Column decoder 3 selectively conducts one switching circuit (not shown) in IO gate circuit 6 by decoding a column address signal CA provided via address buffer 4. Therefore, the data signal is applied to a bit line (not shown) in memory cell array 1. Row decoder 2 decodes a row address signal RA provided via address buffer 4 to selectively activate one word line not shown. Thus, one data signal on a bit line is written into one memory cell (not shown) specified by row decoder 2 and column decoder 3.
In reading operation, a stored data signal is applied on a bit line (not shown) from a memory cell specified by row decoder 2. The data signal on the bit line is amplified by sense refresh amplifier 5. Because column decoder 3 selectively conducts one switching circuit (not shown) in IO gate circuit 6, the amplified data signal is provided to output buffer 8. Thus, data stored in memory cell array 1 is output via output buffer 8.
FIG. 8 is a circuit diagram showing a portion of a conventional bit line peripheral circuit. FIG. 9 is a timing chart for describing the operation shown in FIG. 8. The bit line peripheral circuit of FIG. 8 is described in Digest of Technical Papers, pp. 252-253 of International Solid-State Circuits Conference (ISSCC 85) held in 1985.
Referring to FIGS. 8 and 9, when a word line WLi is activated in reading operation, a switching transistor Qs of a memory cell MC is turned on. Therefore, the data signal stored in a capacitor Cs in memory cell MC appears on a bit line BLj. Because sense amplifier 5 formed by transistors Q1-Q4 is activated in response to activation control signals S.sub.P and S.sub.N, a slight potential difference between bit lines BLj and /BLj is amplified by sense amplifier 5. A column select signal Yj of high level from column decoder 3 is supplied to the gates of transistors Q8 and Q9, whereby transistors Q8 and Q9 are turned on. Therefore, the data signal amplified by sense amplifier 5 is supplied to a pair IO lines 6a and 6b. The data signal on IO line pairs 6a and 6b is sent to output buffer 8.
Although a general read out operation has been described in the foregoing, it is to be noted that a similar operation is carried out in a refresh operation. However, a column select signal Yj of a high level is not provided in a refresh operation, so that transistors Q8 and Q9 are not turned on. The data signal amplified by sense amplifier 5 is applied to capacitor Cs again via a conductive switching transistor Qs. That is to say, although the signal charge held in capacitor Cs gradually decreases in accordance with time, the signal charge is restored by a periodic amplification and rewrite operation by sense amplifier 5. A refresh operation of a DRAM is carried out as described above in a detailed circuit.
FIG. 10 is a circuit block diagram of a refresh control circuit 10 shown in FIG. 7. Referring to FIG. 10, clock signal generator 9 includes a CBR detection circuit 14 for detecting a CAS-before RAS (referred to as "CBR" hereinafter) refresh mode. CBR detection circuit 14 detects a low level of an externally applied column address strobe signal /CAS prior to the fall of an externally applied row address strobe signal /RAS, whereby an externally requested CBR refresh mode is detected. When a CBR refresh mode is detected, CBR detection circuit 14 generates a signal CBR.
Refresh control circuit 10 includes an oscillator 11 for generating a clock signal .phi.i, a timer circuit 12 for generating a refresh clock signal /REFS, and a refresh address counter 13 for generating an internal refresh address signal RFA.
FIG. 11 is a timing chart for describing the operation of the circuit shown in FIG. 10. Referring to FIG. 11, after the fall of signal /CAS at time t3, signal /RAS falls at time t4. CBR detection circuit 14 shown in FIG. 10 supplies signal CBR to oscillator 11 and timer circuit 12.
Oscillator 11 responds to signal CBR to generate a clock signal .phi.i. Timer circuit 12 initiates a self refresh mode operation by detecting a continuation of signal /RAS at a low level for more than a predetermined time length Tw (for example 100 .mu.s) after the provision of signal CBR. More specifically, timer circuit 12 generates a clock signal /REFS for self refresh in response to clock signal .phi.i after time t5 shown in FIG. 11. Clock signal /REFS is applied to clock signal generator 9 and refresh address counter 13.
Therefore, after time t5, refresh address counter 13 counts a self refresh clock signal /REFS to generate a refresh address signal RFA. The refresh address signal RFA is supplied to row decoder 2 via address buffer 4 shown in FIG. 7, whereby a refresh operation of memory cell array 1 is carried out. Self refresh clock signal /REFS has a predetermined period Ps. The increment interval of refresh address signal RFA is determined by the time length of Ps.
At time t8, signals /RAS and /CAS rise, whereby the self refresh operation is completed. After time t8, the DRAM returns to the normal operation mode. Referring to FIG. 11, term Ts indicates a self refresh period (not less than 100 .mu.s), and term Tn indicates a normal operation period.
For a 1 megabit DRAM having an organization of (256 rows.times.256 columns).times.16 bits, the maximum time interval required for 256 memory cells connected to one row is 4 ms, for example. It is necessary to sequentially refresh 256 rows in the memory cell array during this time interval. The refresh period Ps in a self refresh operation is generally set to 8-16 times an externally requested refresh period, for example, a CBR refresh period. The power consumption in a self-refresh operation can be reduced by reducing the number of times of charging a bit line per a unit time. Here, a refresh period is equivalent to a time length from a refresh operation of one row in a memory cell array to the next refresh operation of that row. Presuming that the self refresh period is set to 64 ms, the period Ps of clock signal /REFS shown in FIG. 11 is 250 .mu.s (=64 ms.div.256 rows).
FIG. 12 is a timing chart showing the operation of the circuit of FIG. 11 in a range of a longer time period. Referring to FIG. 12, it is presumed that memory cells of all the rows (for example 256 rows) in the memory cell array are refreshed by an externally requested refresh operation (for example, a CBR refresh) within term Tec starting from time t1 to time t2. During term Tec, 256 rows in the memory cell array are refreshed starting from a beginning row SR1 to a last row LR1.
A self refresh operation is initiated from time t5. During term .DELTA.T0, a starting row SR2 to a last row LR2 are refreshed of the 256 rows in the memory cell array. This time length .DELTA.T0 is equivalent to a self refresh period, i.e. 64 ms in the above-described example. A DRAM in this embodiment is ensured by design that stored data is effectively maintained as long as each memory cell row is refreshed at a time interval of .DELTA.T0.
However, it can be appreciated from FIG. 12 that a last row in the memory cell array is refreshed at time t2 (LR1), and then refreshed at time t6 (LR2). It is apparent that the time length .DELTA.T1 starting from time t2 to time t6 exceeds the time length of .DELTA.T0. This means that the maintenance of the data stored in the last memory cell row is not guaranteed. In other words, the data stored in the last memory cell row may be lost.
Similarly, it is presumed that an externally requested refresh operation is initiated at time t9 after the termination of a self refresh operation at time t8. Therefore, a beginning row SR4 to a last row LR4 of 256 rows in the memory cell array are refreshed during term Tec starting from time t9 until time t10. As a result, the last row in the memory cell array is refreshed at time t6 (LR2), and then the refreshed at time t10 (LR4). It is apparent that the time length of .DELTA.T2 from time t6 to time t10 is longer than the time length of .DELTA.T0. Therefore, the data stored in the last memory cell row may be lost.
In order to prevent stored data from being lost, the time length from time t2 to t4 shown in FIG. 12 was limited to be not so longer than time length .DELTA.T1 in a conventional DRAM. That is to say, operational limitation in an external circuit was required.